We have made a 16 bit processor with less than 2000 gates. The first version was implemented on an ACTEL A1020, the current version uses a XILNIX 3090. A complete computer was built with this processor make use of only self developed components implemented on XILINX FPGAs (video controller, scsii controller, parallel and serieal interface, keyboard interface) and a multitasking operating system was written. +-------+ | XPROZ | +-------+ HARDWARE INTERFACE: ================== A14-A0: address bus (seperate 32k words = 64 kbyte RAM, ROM and I/O address range) D15-D0: data bus RAMSEL~: if 0: accessing RAM (processor address $0000-$7fff) ROMSEL~: if 0: accessing ROM (processor address $8000-$ffff) IOSEL~: if 0: accessing I/O space RW~: if 0: write if 1: read OE~: if 0: RAM/ROM output buffers enabled RESET~: if 0: reset processor (program starts at address $8000 in in interrupt mode 5 with disabled interrupts (sr=$00) IRQ1~: if 0: interrupt request 1 (must be asserted at least 17*8 clock cycles) IRQ2~: if 0: interrupt request 2 (must be asserted at least 17*8 clock cycles) IRQ3~: if 0: interrupt request 3 (must be asserted at least 17*8 clock cycles) IRQ4~: if 0: interrupt request 4 (must be asserted at least 17*8 clock cycles) IRQ5~: if 0: interrupt request 5 (must be asserted at least 17*8 clock cycles) CLK: processor clock (internaly divide by 8) PROGRAM COUNTER (pc): ==================== The processor has no pc register. Memory location 0 is used for user pc and memory location i (1<=i<=5) is used in interrupt mode i. STATUS REGISTER (sr): ==================== This is the only internal processor register. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | - | i5| i4| i3| i2| i1| ie| - | - | - | - | V | N | Z | C | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ie: if 1: interrupt enabled i5: if 0: processor is in interrupt mode 5 (highest priority) (memory location 5 is used as pc) i4: if 0 and i5=1: processor is in interrupt mode 4 (memory location 4 is used as pc) i3: if 0 and i5=i4=1: processor is in interrupt mode 3 (memory location 3 is used as pc) i2: if 0 and i5=i4=i3=1: processor is in interrupt mode 2 (memory location 2 is used as pc) i1: if 0 and i5=i4=i3=i2=1: processor is in interrupt mode 1 (memory location 1 is used as pc) V: overflow flag N: negativ flag Z: zero flag C: carry flag i5 - i1 are cleared by the external signals IRQ5~ - IRQ1~. They are set (switch back to user mode) under software control. After a reset the sr contains $00. INSTRUCTION FORMAT: ================== B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |XSR|XIO|ZSR|ZIO| | | | | | | +---------------+BED|SF |Z1 Z0 |Y1 Y0 |X1 X0 |ALU ALU ALU ALU| | CC | | | | | | 3 2 1 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | x address (optional) | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | y address (optional) | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | z address (optional) | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ALU function determind by ALU3, ALU2, ALU1, ALU0 ------------------------------------------------ +------+----------------+------+-------------------+ | ALU | | ALU | | | 1 0 | | 3 2 | | +------+----------------+------+-------------------+ | | | 0 0 | add | | 0 0 | arithmetic | 0 1 | sub | | | | 1 0 | addc | | | | 1 1 | subc | +------+----------------+------+-------------------+ | | | 0 0 | nor | | 0 1 | logic | 0 1 | and | | | | 1 0 | eor | | | | 1 1 | or | +------+----------------+------+-------------------+ | | | 0 0 | ror | | 1 0 | shift right | 0 1 | rorc | | | | 1 0 | asr | | | | 1 1 | lsr | +------+----------------+------+-------------------+ | | | 0 0 | rol | | | shift left | 0 1 | rolc | | 1 1 | | 1 0 | asl=lsl | | +----------------+------+-------------------+ | | byte swap | 1 1 | bswp | +------+----------------+------+-------------------+ 1. operand: x determind by X1,X0 -------------------------------- +-------+----------------------------------------------+---------+ | B5 B4 | description | symbol | +-------+----------------------------------------------+---------+ | 0 0 | no x operand (internal a 1 is used) | - | | 0 1 | x is an immediate operand | #wert | | 1 0 | address of x | wert | | 1 1 | address of address of x | (wert) | +-------+----------------------------------------------+---------+ 2. operand: y determind by Y1,Y0 -------------------------------- +-------+----------------------------------------------+---------+ | B7 B6 | description | symbol | +-------+----------------------------------------------+---------+ | 0 0 | no y operand (internal a 0 is used) | - | | 0 1 | y is an immediate operand | #wert | | 1 0 | address of y | wert | | 1 1 | address of address of y | (wert) | +-------+----------------------------------------------+---------+ result: z determind by Z1,Z0 ---------------------------- +-------+----------------------------------------------+---------+ | B9 B8 | description | symbol | +-------+----------------------------------------------+---------+ | 0 0 | no result | - | | 0 1 | result has same address as y operand | = | | 1 0 | address of z | wert | | 1 1 | address of addresse of z | (wert) | +-------+----------------------------------------------+---------+ exception: For y=(00) and z=(01) (i.e. no y operand and result has same address as y operand) the result is stored in the actual pc (0 in user mode, i in interrupt mode i). This allows 2 word jump instruction. e.g. add cs hf #label,-,= NOTE: The combination y=(01) and z=(01) (i.e. y operand is immediate operand and result has same address as y operand) overwrites the immediate operand with the result (self modifying code). This can be used for loop counter. add tr hf #100,-,lab2+1 ; initialise counter lab1: ... ... ... lab2: sub tr sf -,#0,= ; subtract 1 add ne hf #lab1,-,= ; jump if not 0 ... set flags: determind by SF --------------------------- +----+----------------------------------------------------+---------+ |B10 | description | symbol | +----+----------------------------------------------------+---------+ | 0 | flags are not modified | hf | | 1 | flags are modified according the result | sf | +----+----------------------------------------------------+---------+ conditional/unconditional: determind by BED ------------------------------------------- +----+----------------------------------------------------+---------+ |B11 | description | symbol | +----+----------------------------------------------------+---------+ | 0 | Instruction is ececuted only if the condition |gt,ne,...| | | CC (B15-B12) is is satisfied | | | 1 | Instruction is always executed; B15-B12 | | | | modifies the x operand and result address | tr | +----+----------------------------------------------------+---------+ condition code: determind by CC ------------------------------- +---------------+------+---------------------+----------------------+ |B15 B14 B13 B12|symbol| description | function | +---------------+------+---------------------+----------------------+ | 0 0 0 0 | me | minus or equal | Z+N | | 0 0 0 1 | pe | plus and not equal | (~Z)(~N) | | 0 0 1 0 | hi | higher | (~C)(~Z) | | 0 0 1 1 | ls | lower or same | C+Z | | 0 1 0 0 | cc | carry clear | ~C | | 0 1 0 1 | cs | carry set | C | | 0 1 1 0 | ne | not equal | ~Z | | 0 1 1 1 | eq | equal | Z | | 1 0 0 0 | vc | overvlow clear | ~V | | 1 0 0 1 | vs | overflow set | V | | 1 0 1 0 | pl | plus | ~N | | 1 0 1 1 | mi | minus | N | | 1 1 0 0 | ge | greater or equal | NV+(~N)(~V) | | 1 1 0 1 | lt | less then | N(~V)+(~N)V | | 1 1 1 0 | gt | greater then | NV(~Z)+(~N)(~V)(~Z) | | 1 1 1 1 | le | less or equal | Z+N(~V)+(~N)V | +---------------+------+---------------------+----------------------+ status register as x operand: determind by XSR ---------------------------------------------- +----+----------------------------------------------------+---------+ |B15 | description | symbol | +----+----------------------------------------------------+---------+ | 0 | the regular x operand is used | none | | 1 | bits 13-8,3-0 of the regular x operand are | | | | replaced by the corresponding bits in the | & | | | status register | | +----+----------------------------------------------------+---------+ x operand from I/O address space: determind by XIO -------------------------------------------------- +----+----------------------------------------------------+---------+ |B14 | description | symbol | +----+----------------------------------------------------+---------+ | 0 | the regular x operand is used | none | | 1 | the address of the x operand is an I/O address | | | | (no action if no x operand or immediate operand) | @ | +----+----------------------------------------------------+---------+ result stored in status register: determind by ZSR -------------------------------------------------- +----+----------------------------------------------------+---------+ |B13 | description | symbol | +----+----------------------------------------------------+---------+ | 0 | the result is stored normaly | none | | 1 | the result is stored normaly and in the status | | | | register | & | +----+----------------------------------------------------+---------+ NOTE: The least significant bits (flags) are stored in the status register only if also SF=1. The upper byte (interrupt and interrupt enable flags) are stored in the status register only if there is also a normal Z result (in memory or I/O, but not the current programm counter i.e. no Y operand and Z result equal Y operand). EXAMPLE: and tr sf &-,#0,&- ; C,Z,N,V flags cleared ; interrupt flags not changed and tr hf &-,#0,&10 ; C,Z,N,V flags not changed ; interrupt flags cleared and tr sf &-,#0,&10 ; C,Z,N,V flags and interrupt flags cleared result stored in I/O address space: detemind by ZIO --------------------------------------------------- +----+----------------------------------------------------+---------+ |B12 | description | symbol | +----+----------------------------------------------------+---------+ | 0 | the result is stored normaly | none | | 1 | the address of the result is an I/O address | | | | (no action if no result) | @ | +----+----------------------------------------------------+---------+ INSTRUCTION SUMMARY =================== add x,y,z z = x + y C = carry Z = nor(z[i]) N = z[15] V = overflow addc x,y,z z = x + y + C C = carry Z = nor(z[i]) N = z[15] V = overflow sub x,y,z z = y - x C = carry Z = nor(z[i]) N = z[15] V = overflow subc x,y,z z = y - x - C C = carry Z = nor(z[i]) N = z[15] V = overflow nor x,y,z z = x nor y C = 0 Z = nor(z[i]) N = z[15] V = undefined or x,y,z z = x or y C = 0 Z = nor(z[i]) N = z[15] V = undefined and x,y,z z = x and y C = 0 Z = nor(z[i]) N = z[15] V = undefined eor x,y,z z = x eor y C = 0 Z = nor(z[i]) N = z[15] V = undefined rol x,y,z z[0] = x[15] C = x[15] z[i] = x[i-1] for 1 <= i <= 15 Z = nor(z[i]) N = z[15] V = undefined rolc x,y,z z[0] = C C = x[15] z[i] = x[i-1] for 1 <= i <= 15 Z = nor(z[i]) N = z[15] V = undefined lsl x,y,z asl x,y,z z[0] = 0 C = x[15] z[i] = x[i-1] for 1 <= i <= 15 Z = nor(z[i]) N = z[15] V = undefined ror x,y,z z[i] = x[i+1] for 0 <= i <= 14 C = x[0] z[15] = x[0] Z = nor(z[i]) N = z[15] V = undefined rorc x,y,z z[i] = x[i+1] for 0 <= i <= 14 C = x[0] z[15] = C Z = nor(z[i]) N = z[15] V = undefined lsr x,y,z z[i] = x[i+1] for 0 <= i <= 14 C = x[0] z[15] = 0 Z = nor(z[i]) N = z[15] V = undefined asr x,y,z z[i] = x[i+1] for 0 <= i <= 14 C = x[0] z[15] = x[15] Z = nor(z[i]) N = z[15] V = undefined bswp x,y,z z[i] = x[i+8] for 0 <= i <= 7 C = x[15] z[i] = y[i-8] for 8 <= i <= 15 Z = nor(z[i]) N = z[15] V = undefined program example: add tr hf #100,xwert,ywert ; add 100 to xwert and store result in ; ywert; flags not modified add cs sf -,ywert,= ; add 1 to ywert if carry set ; modify flags according the result add mi hf #l1,-,= ; jump to l1 if negativ flag is set or tr hf @$20,#$20,(30) ; uncoditional 'or' with flags unchaged ; 1. operand ist from I/O address $20 ; 2. operand = $20 (decimal 32) ; the address of the result memory location ; is stored im memory location 30 l1: or tr hf &#$3333,-,xwert ; replace bits 13-8 and 3-0 of the number ; $3333 with the coresponding bits of the ; status register and store result in xwert ; flags not modified l2: add tr hf #l2,-,= ; endless loop ; IMPLEMENTATION DETAILS ---------------------- +-------------*-------------*------------------------------DIN[15:0] | | | +---------+ | | | + TAKTE + +-----+-------*-----+-------*-----+---------+ |T0 T1 T2 +--CLK | +---v--+ | +---v--+ | +---v--+ | +-v--v--v-+ +-> XREG <-+ +-> YREG <-+ +-> BREG <-+ +---------* | | +---v--+ | +---v--+ | +---v--+ | +--v--v--v--+ | | | | | +----EB-----< | | | | +--------+---------EY-----< | | +--------+-------------+---------EX-----< | +---+ | +--*----------+ | | | | |A |B | | +---B[15:0]------> | | +-v----v-+ +---v---+ +---v---+ | <-IRQ0 | \ XMUX /<+ | YGATE <-+ | AGATE <--GA,ADR[2:0]--< <-IRQ1 | +-v+ | +---v---+ | +---v---+ | <-IRQ2 | | | | | | | <-IRQ3 | | | | +-------+------GY-----------< <-IRQ4 | | +-------+-------------+------GX[1:0]------< <-IRQ5 | |X |Y | | control | | +---v----, ,----v---+ | | | | \ \/ / | | >-OE *-SR0>\ ALU /<-----------+------ALU [4:0]----< >-RW | +-v---v----+ | | >-BE | | |Z | | >-IO | +---+-------------------+------SR_IN[15:0]--> >-MEM +-------------+-------------------+------SR[15:0]-----< | | | +-----------+ | | | +---------------------------------AOUT[15:0] +-----------------------------------------------------DOUT[15:0] +-----+--------------------+----------------------------------------------+ |phase| function | description | +-----+--------------------+----------------------------------------------+ | 0 | PC -> y | load PC | | 1 | (y) -> BREG | read opcode | | 2 | y+1 -> PC,y | PC+1 | | 3 | y+1 -> PC | PC+1 | | 4 | (y) -> y | read address of address of x operand | | 5 | (y) -> y | read address of x operand | | 6 | (y) -> x | read x operand | | 7 | PC -> y | load PC | | 8 | y+1 -> PC | PC+1 | | 9 | (y) -> y | read ((address of) address of) y operand | | 10 | (y) -> y | raed address of y operand | | 11 | (y) -> y | read y operand | | 12 | ALU -> x | do ALU operation, result -> x | | 13 | PC -> y | load pc | | 14 | y+1 -> PC | PC+1 | | | -> y if ~CC | PC+1 | | 15 | (y) -> y | read (address of) address of result | | 16 | (y) -> y | read address of result | | 17 | x -> (y) | store result | +-----+--------------------+----------------------------------------------+ x: XREG y: YREG CC: 1 if condition code true ALU: output of ALU PC: program counter = memory location 0 for user mode, i for interrupt mode i +----+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |phas| EB| EY| EX| GY|GX1|GX0| GA|Ad2|Ad1|Ad0|AL4|AL3|AL2|AL1|AL0| IO|MEM| RW| +----+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | - | 1 | - | - | - | - | 0 | f1| f5| f6| - | - | - | - | - | 1 | 0 | 1 | | 1 | 1 | 0 | - | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 | | 2 | 0 | 1 | - | 1 | 1 | 0 | 0 | f1| f5| f6| - | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | 3 | 0 | 0 | - | 1 | 1 | 0 | 0 | f1| f5| f6| - | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | 4 | 0 | 1 | - | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 | | 5 | 0 | 1 | - | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 | | 6 | 0 | - | 1 | - | - | - | 1 | - | - | - | - | - | - | - | - |~f8| f8| 1 | | 7 | 0 | 1 | 0 | - | - | - | 0 | f1| f5| f6| - | - | - | - | - | 1 | 0 | 1 | | 8 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | f1| f5| f6| - | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | 9 | 0 | 1 | 0 | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 | | 10 | 0 | 1 | 0 | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 | | 11 | 0 | 1 | 0 | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 | | 12 | 0 | - | 1 | f2| f3| f4| 0 | f1| f5| f6| f7| B3| B2| B1| B0| 1 |f10| 0 | | 13 | 0 | 1 | 0 | - | - | - | 0 | f1| f5| f6| - | - | - | - | - | 1 | 0 | 1 | | 14 | 0 |~CC| 0 | 1 | 1 | 0 | 0 | f1| f5| f6| - | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | 15 | 0 | 1 | 0 | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 | | 16 | - | 1 | 0 | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 | | 17 | - | - | - | 0 | 1 | 1 | 1 | - | - | - | - | 0 | 0 | 0 | 0 |~f9| f9| 0 | +----+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ f1 = (~I5) + (~I4) f2 = B6 + B7 f3 = ~(B11 & B15) f4 = B4 + B5 f7 = B13 & B11 f8 = B11 & B14 & B5 f5 = ( (~I2) + (~I3) ) & I4 & I5 f9 = B11 & B12 f6 = (~I1) & I2 & I4 + (~I3) & I4 + (~I5) f10= (~CC)+(~B8)+B9+B6+B7 B= instruction bit i CC = 1 if condition code true I= sr[8+n] P= phase i control signals: --------------- EB = P1 EY = ~(P1 + P3 + P8 + P14 & CC) EX = P6 + P12 GY = ~(P12 & (~B6) & (~B7) + P17) GX1= ~(P12 & B11 & B15) GX0= P12 & (B4+B5) + P17 GA = ~(P0 + P2 + P3 + P7 + P8 + P12 + P13 + P14) ADR2 = (~I5) + (~I4) ADR1 = ( (~I2) + (~I3) ) & I4 & I5 Adr0 = (~I1) & I2 & I4 + (~I3) & I4 + (~I5) ALU4 = B13 & B11 ALU3 = P12 & B3 ALU2 = P12 & B2 ALU1 = P12 & B1 ALU0 = P12 & B0 RW = ~(P2 + P3 + P8 + P12 + P14 + P17) IO = ~(P6 & B11 & B14 & B5 + P17 & B11 & B12) MEM= P6 & B11 & B14 & B5 + P17 & B11 & B12 + P12 & ( (~CC)+(~B8)+B9+B6+B7 ) CLOCK: ----- .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. . | |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| +---------------+ +---------------+ T0 -------+ +---------------+ +------------ +---+ +---+ T1 -------+ +---------------------------+ +------------------------ +-------+ +-------+ + T2 ---+ +-----------------------+ +-----------------------+ state transition table: ---------------------- B= instruction bit i CC = 1 if condition code true P= phase i C9,C8 = B9,B8 if B9,B8 <> 0,1 C9,C8 = B7,B6 if B9,B8 = 0,1 P0 --> P1 P1 --> P2 P2 --> P3 if B4+B5 --> P8 if (~(B4+B5)) & (B6+B7) & ((~B8)+B9) --> P9 if (~(B4+B5)) & (B6+B7) & B8 & (~B9) --> P12 if (~(B4+B5)) & (~(B6+B7)) P3 --> P4 if B4 & B5 --> P5 if (~B4) & B5 --> P6 if B4 & (~B5) P4 --> P5 P5 --> P6 P6 --> P7 if B6+B7 --> P12 if ~(B6+B7) P7 --> P8 if (~B8)+B9 --> P9 if B8 & (~B9) P8 --> P9 P9 --> P10 if B6 & B7 --> P11 if (~B6) & B7 --> P12 if (~B7) P10 --> P11 P11 --> P12 P12 --> P13 if C9+C8 --> P0 if (~C9) & (~C8) P13 --> P14 P14 --> P15 if CC & C9 --> P17 if CC & (~C9) --> P1 if ~CC P15 --> P16 if C8 --> P17 if ~C8 P16 --> P17 P17 --> P0 +---+ +----->| 4 | | +-.-+ | v | +---+ | +--->| 5 | | | +-.-+ | | v +'-'+ +---+ +---+ +--->| 3 |-->| 6 |-->| 7 |---+ | +---+ +.--+ +-.-+ | | | v | | | +---+ | | +-----------+----->| 8 |-+ | | | | +---+ v v +---+ +---+ +'-'+ | +---+ +---+ | 0 |->| 1 |->| 2 +----------+---------->| 9 |->| 10| +---+ +---+ +-.-+ | +.-.+ +-.-+ ^ ^ ^ | | +----------+ | | | | | | v v v | | | | | +---+ +---+ | | | | +---------->| 12|<-------| 11|<---+ | | | +.-.+ +---+ | +-----+-------------------+ v | | +---+ | | | 13| | | +-.-+ | | v | | +---+ | +------------------| 14|-----+ | +-.-+ v | | +---+ | | | 15| | | +.-.+ | | +----+ v | | | +---+ | | | | 16| | v v +-.-+ | +---+ | +---------------------------| 17|<----+ +---+ data and reset signals for state flip-flops: ------------------------------------------- D0 = P12 & (~C9) & (~C8) + P17 D1 = P0 + P14 & (~CC) D2 = P1 D3 = P2 R3 = P8 + P9 + P12 D4 = P3 R4 = P5 + P6 D5 = P4 + P3 & (~B4) D6 = P5 + P3 & (~B5) D7 = P6 R7 = P12 D8 = P7 + P2 & ( ~(B4+B5) ) R8 = P9 +P12 D9 = P8 + D8 & B8 & (~B9) R9 = P12 D10= P9 R10= P11 + P12 D11= P10 + P9 & (~B6) R11= P12 D12= (P2 & ( ~(B4+B5) ) + P6 ) & ( ~(B6+B7) ) + P9 & (~B7) + P11 D13= P12 R13=P0 D14= P13 D15= P14 R15= P1 + P17 D16= P15 R16= P17 D17= P14 & (~C9) + P15 & (~C8) + P16 R17= P1 description of the functional units: =================================== 1. XREG ------- description: 16 bit register inputs: D[15:0], CLK, E outputs: Q[15:0] function: if E=1 then D[15:0] is latched into the register with the next rising clock reset: after a reset this register contains 0 2. YREG ------- description: 16 bit register inputs: D[15:0], CLK, E outputs: Q[15:0] function: if E=1 then D[15:0] is latched into the register with the next rising clock reset: after a reset this register contains $8000 3. BREG ------- description: 16 bit register inputs: D[15:0], CLK, E outputs: Q[15:0] function: if E=1 then D[15:0] is latched into the register with the next rising clock reset: after a reset this register contains 0 4. TAKTE -------- description: clock divider inputs: CLK outputs: T0, T1, T2 funcion: generates the following clock signals: .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. . CLK| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| +---------------+ +---------------+ T0 -------+ +---------------+ +------------ +---+ +---+ T1 -------+ +---------------------------+ +------------------------ +-------+ +-------+ + T2 ---+ +-----------------------+ +-----------------------+ ^ start after reset reset: during reset T0, T1 and T2 are 0 5. XMUX ------- description: multiplexer, which outputs $0001, the status register or the contens of XREG inputs: A[15:0], B[15:0], G1, G0 outputs: C[15:0] function: G1 G0 | C[15:14] | C[13:8] | C[7:4] | C[3:0] --------------------------------------------- 0 0 | 00 | A[13:8] | 0 | A[3:0] 0 1 | B[15:14] | A[13:8] | B[7:4] | A[3:0] 1 0 | 00 | 000000 | 0000 | 0001 1 1 | B[15:14] | B[13:8] | B[7:4] | B[3:0] 6. YGATE -------- description: multiplexer, which outputs $0000 or the contens of YREG inputs: A[15:0], G outputs: C[15:0] funktion: G | C[15:0] ------------ 0 | $0000 1 | A[15:0] 7. AGATE -------- description: multiplexer, which outputs $0000, $0001, $0002, $0003, $0004, $0005 or the contens of YREG inputs: A[15:0], G,S2,S1,S0 outputs: C[15:0] function: if G=1 : C[15:0]=A[15:0] if G=0 : C=0 for 15 <= i <= 3 C2=S2 C1=S1 C0=S0 8. ALU ------ description: does arithmetic and logical operations inputs: X[15:0], Y[15:0], CIN, S[4:0] outputs: Z[15:0], SR_OUT[15:0] function: +------------+------------+---------------------------+ |s1 s0 s3 s2 | Z | CF VF | +------------+------------+---------------------------+ | 0 0 0 0 | X+Y | C(X+Y) V(X+Y) | | 0 0 0 1 | Y-X | C(Y-X) V(Y-X) | | 0 0 1 0 | X+Y+CIN | C(X+Y+CIN) V(X+Y+CIN | | 0 0 1 1 | Y-X-CIN | C(Y-X-CIN V(Y-X-CIN) | +------------+------------+---------------------------+ | 0 1 0 0 | X nor Y | 0 V(X+Y) | | 0 1 0 1 | X and Y | 0 V(Y-X) | | 0 1 1 0 | X eor Y | 0 V(X+Y+CIN | | 0 1 1 1 | X or Y | 0 V(Y-X-CIN) | +------------+------------+---------------------------+ | 1 0 0 0 | ror X | X[0] V(X+Y) | | 1 0 0 1 | rorc X | X[0] V(Y-X) | | 1 0 1 0 | asr X | X[0] V(X+Y+CIN | | 1 0 1 1 | lsr X | X[0] V(Y-X-CIN) | +------------+------------+---------------------------+ | 1 1 0 0 | rol X | X[15] V(X+Y) | | 1 1 0 1 | rolc X | X[15] V(Y-X) | | 1 1 1 0 | asl X | X[15] V(X+Y+CIN | | 1 1 1 1 | bswp X,Y | X[15] V(Y-X-CIN) | +------------+------------+---------------------------+ if S4=1: SR_OUT[13:8,3:0]= Z[13:8,3:0] if S4=0: SR_OUT[0] = CF SR_OUT[1] = nor (Z[i]) i=0..15 SR_OUT[2] = Z[15] SR_OUT[3] = VF SR_OUT[13:8] = Z[13:8]